1. Field of Invention
This invention relates to a fabrication method for multilevel interconnects. More particularly, the present invention relates to a fabrication method for a damascene structure that comprises an air-gap type of dielectric layer.
2. Description of Related Art
The conventional fabrication method for interconnects includes depositing a metal layer on an insulation layer, for example, a silicon oxide layer, wherein the insulation layer is used to isolate the metal layer. The metal layer is then defined to a pre-determined pattern of a conductive line, followed by forming a vertical via opening between the layers of conductive line. A conductive layer of similar or different material from the metal layer further fills the via opening to complete the vertical connection between the layers of conductive line. A point that is worth noting is, as the number of layers of conductive line in an integrated circuit increases, the metal layer design with two layers and above gradually becomes the method to use in the fabrication of many integrated circuits. The metal layers are isolated by inter-metal dielectrics (IMD) and a via is used to connect the upper and the lower metal layers of conductive lines.
A majority of the conventional inter-metal dielectric layer is the plasma-enhanced chemical vapor deposited (PECVD) silicon oxide or the low dielectric constant dielectric layer. The dielectric constant for a silicon oxide dielectric layer is, however, too high and parasitic capacitance tends to generate between the metal interconnects. On the other hand, the dielectric layer with a low dielectric constant normally does not have sufficient mechanical strength, which poses a great challenge when chemical mechanical polishing is conducted. Moreover, the low dielectric constant dielectric layer does not have very stable thin film property. As a result, the problems of out-gassing and peeling often occur. Additionally, the low dielectric constant dielectric layer needs to be cleaned under oxygen-free plasma after etching to prevent the pattern from being damaged. The manufacturing process, thereby, becomes more complicated.
The invention provides a fabrication method for a damascene structure, wherein the inter-metal dielectric layer comprises a low dielectric constant and a high mechanical strength.
The present invention provides a fabrication method for an inter-metal dielectric layer, wherein silicon oxide is the major component for the inter-metal dielectric layer to improve the problems of the conventional low dielectric constant materials.
The present invention provides a fabrication method for a damascene structure, wherein a substrate already comprising a first conductive layer is provided. A silicon nitride type of a first dielectric layer is then formed on the substrate, followed by patterning the first dielectric layer to form a trench like structure. A silicon oxide type of a second dielectric layer is then formed on the first dielectric layer and in the trench like structure. The second dielectric layer is planarized until the surface of the first dielectric layer is exposed. The first dielectric layer is further removed to form a trench, followed by filling the trench with a second conductive layer.
According to the fabrication method for a dual damascene structure of the present invention, a substrate comprising a first conductive layer is provided. A silicon oxide type of a first dielectric layer and a silicon nitride type of a second dielectric layer are sequentially formed on the substrate. The second dielectric layer is then patterned to form a trench like structure. A silicon oxide type of third dielectric layer is then formed on the second dielectric layer and in the trench like structure, wherein an air-gap is concurrently formed in the third dielectric layer in the trench like structure. The third dielectric layer is then planarized until a surface of the second dielectric layer is exposed. The second dielectric layer is then removed to form a trench. The first dielectric layer is patterned to form a via opening to expose the first conductive layer, wherein the via opening and the trench together form a dual damascene opening. A second conductive layer subsequently fills the dual damascene opening.
According to the present invention, an air-gap is formed in the dielectric layer to lower the dielectric constant of the dielectric layer and to reduce the parasitic capacitance between the interconnects.
The present invention employs silicon oxide as a major component for the dielectric layer, wherein its mechanical strength and thin film property are better than other low dielectric constant materials.
According to the present invention, the depth of the trench is determined by the thickness of the deposited silicon nitride dielectric layer. A trench having a non-uniform depth resulted from inconsistent etching rates due to the various trench widths and trench density as in the conventional practice is thus prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.